1. Field of the Invention
The present invention generally relates to a CMOS image device, and more particularly to an image sensor device with photo-diode on CMOS transistors.
2. Description of the Prior Art
Semiconductor image sensors are categorized into two kinds: CMOS sensor and charged-coupled device (CCD). Traditionally, CCD-based image devices are relatively expensive and have high power dissipation levels; thus, there is much interest in building single chip image device using standard CMOS process, which would promote integration and low power consumption.
A general photocell, that can be used in an active pixel sensor array, consists of a photodiode acting as a light sensor, a reset MOS acting as resetting a storage node and the photodiode potential, a source follower MOS and a row select MOS.
FIG. 1A is a cross sectional view showing a structure of a CMOS image sensor according to the prior art. A general photocell, that can be used in an active pixel sensor array, consists of a photodiode acting as a light sensor, a reset MOS device acting as resetting a storage node and the photodiode potential, a source follower MOS device and a row select MOS device. An epitaxial layer 110 is on a semiconductor substrate 100. The P-well 210 is in the semiconductor substrate 100. A reset MOS device comprises a first source terminal 240, a first drain terminal 520 and a first gate substrate 300 in and on a P-well 210. The first drain terminal 520 acts as an area collecting incident light. A source follower MOS device is adjacent to a row select MOS device. The source follower MOS device comprises a second source 260 and a second gate structure 310 in and on the P-well 210. The row select MOS device comprises a third gate 320 and a third drain terminal 280 on and in the P-well 210. A drain/source region 270 comprises a drain terminal of the source follower MOS device and a source terminal of the row select MOS device.
A first isolation device 430 is between the first drain terminal 520 of the reset MOS device and the second source terminal 260 of the source follower MOS device. And a second isolation device 440 is between the third drain terminal 280 of the row select MOS device and outside device. A dielectric layer 410 covers all surfaces of the semiconductor substrate 100 and all MOS devices except the portions of the first drain terminal 520 and the second gate structure 310. The conductor 730 covers the portion surface of the semiconductor substrate 100 and electrically contacts the first drain terminal 520 and the second gate structure 310.
FIG. 1B is a top view showing a layout of a unit pixel of a CMOS image sensor according to the prior art. A first region 500 represents the reset MOS device. A second region 330 represents the source follower MOS device and a third region 700 is the row select MOS device. A fourth region 900 is the conductor connecting the source follower 330. A discharged voltage Vdd connects a fifth region 400. A dielectric region 410 covers all surfaces of the CMOS image sensor.
FIG. 1C depicts a generic realization of a photocell that can be used in an active pixel array in the prior art. Initially, a positive reset signal is applied to a gate of a reset MOS 500, which turns on as a result and resets the voltage across the photodiode to some preset value near the discharged voltage. The measurement of light energy is accomplished by turning off the reset MOS 500 and letting the voltage change across the photodiode discharge in response to the light energy failing on it. The actual signal due to the amount of illumination falling on the photodiode during the integration period is the difference between the voltage measured at the end of the integration period and the output voltage obtained after turning on the reset MOS 500 to reset the photodiode voltage to the preset value. After a predetermined integration time the voltage level across the photodiode is amplified by a source follower MOS 330 and sampled at an output node 800 of row select MOS 700.
Moreover, the prior photocell is formed by building the photodiode and three MOS devices on a horizontal level area, and all source and drain regions in the P-well results in large consumption of dimensions. Furthermore, the photodiode resetting potential in the prior photocell is not more than the discharged voltage and restricts the quantum efficiency of photodiode.
In accordance with the present invention, a CMOS image device comprised a photocell and two transistors.
It is further object of this invention that a structure of amorphous silicon is used as the area of a photocell for collecting incident light.
It is another object of this invention that a CMOS image sensor is arranged in a modified area that can both reduce the pixel size and maintain sensitivity of the image sensor.
In the present invention, a CMOS image device has a semiconductor substrate of a first conductivity whereon comprises an epitaxial layer formed. A first MOS device acting as a source follower of an active pixel has a source terminal connected to supply voltage, a drain terminal, and a gate structure in and on the semiconductor substrate. A second MOS device acting as a row select of the active pixel has a source terminal, a drain terminal connected to an output device and a gate structure in and on the semiconductor substrate, and the source terminal is adjacent to the drain terminal of the first MOS device. A first dielectric layer such as a silicon nitride layer covers all the upper surfaces of the first MOS device, the second MOS device and the semiconductor substrate except the portion of the surface of the gate structure of the first MOS device. A polysilicon layer is on the first dielectric layer and electrically contacts the gate structure of the first MOS device. An amorphous silicon layer acting as a photo-diode area for collecting incident light is on the polysilicon layer. Near the surface of the polysilicon layer, the amorphous silicon layer has the dopants of a second conductivity opposite to the first conductivity, while has dopants of the first conductivity near the upper surface thereof. Furthermore, an electric node is on the amorphous silicon layer. A second dielectric layer such as an oxide layer covers the amorphous silicon layer and the electric node. A via plug structure is in a via hole through the second dielectric layer and the via plug structure electrically connects the electric node and ground or bias voltage outside. A contact plug structure is in a contact window through the second dielectric layer, the amorphous silicon layer, the polysilicon layer and the first dielectric layer. The contact plug structure connects electrically the gate structure of the second MOS device. Besides, the CMOS image device further comprises a first well and a second well of the second conductivity in the semiconductor substrate, and the all MOS devices between the first well and the second well. A first diffusion region is both in the first well and under the surface of the semiconductor substrate and contacts electrically the polysilicon layer. A second diffusion region is both in the second well and under the surface of the semiconductor substrate and contacts electrically the polysilicon layer. Then a first isolation device is between the first diffusion region and the first source terminal. A second isolation device is between the diffusion region and the second drain terminal.